This invention relates to methods and circuits for providing an output clock signal with a frequency related to the frequency of an input clock signal.
Circuits may require clock signals with different frequencies for their operation. While multiple clock generation circuits may be used to produce clocks of different frequencies, the clock signals produced by the different clock circuits are generally not synchronized. In addition, the clock generation circuits require added circuitry, and occupy additional on-chip area. In integrated circuit implementations, the multitude of independent clock signals may require numerous input/output circuits to transmit the clock signals to other circuits or devices external to the integrated circuit.
Clock division circuits may be used to generate clock signals of different frequencies from a single input clock signal. The clock division circuits may require less circuitry and on-chip area than multiple clock generation circuits. In integrated circuits, the use of clock division circuitry requires only a single clock to be generated and/or received by the circuit. The integrated circuit may therefore require less input/output circuitry, as only a single clock need be received or transmitted. In addition, as the clock signals produced by clock division circuits are all dependent on the same input clock, the frequencies of the output clock signals are precisely synchronized.
Clock division circuits that produce clock signals with frequencies related to each other by particular integer ratios are well known. Clock division circuits that produce clock signals in non-integer ratios may rely on phase-locked loops (PLL) for their operation. Such clock division circuits may require large amounts of circuitry for their operation.
Improved clock division methods and circuits operative to produce output clock signals related by non-integer frequency ratios and requiring small amounts of circuitry are needed.